TY - GEN
T1 - Thermo-mechanical modelling and thermal performance characterisation of a 3-D folded flex module
AU - Majeed, Bivragh
AU - Kelley, Matthew
AU - Van Sinte Jans, Jean Baptiste
AU - Paul, Indrajit
AU - Slattery, Orla
AU - Barton, John
AU - O'Mathuna, Sean C.
AU - O'Flynn, Brendan
AU - Malshe, Ajay P.
PY - 2006
Y1 - 2006
N2 - This paper reports the initial investigation into the thermo mechanical stress and thermal performance of a folded flexible substrate module. The module consists of flip chip bare die silicon onto a flex and interconnected via conductive adhesive and folding the flex to obtain the final module. From the FEM analysis it was concluded that the stresses in silicon and conductive adhesive are not significant to cause potential reliability problems. The model showed that for 525 and 250 microns thick silicon chip the stresses do not vary notably with change in polyimide or copper thickness but vary significantly below this critical value. This shows that silicon is the dominant material in the stack when the chip thickness is above 100 microns but below this thickness, stress is more dependent on copper and polyimide thickness. Thermal performance characterisation showed that for the current module set-up total power to the module rather then power to the individual chip is an important criterion for the selection of thermal management scheme. Changing the thickness of polyimide and copper has little effect on module temperature. Decreasing the chip thickness increases the thermal density and thereby increases the total temperature for the stack for any given power.
AB - This paper reports the initial investigation into the thermo mechanical stress and thermal performance of a folded flexible substrate module. The module consists of flip chip bare die silicon onto a flex and interconnected via conductive adhesive and folding the flex to obtain the final module. From the FEM analysis it was concluded that the stresses in silicon and conductive adhesive are not significant to cause potential reliability problems. The model showed that for 525 and 250 microns thick silicon chip the stresses do not vary notably with change in polyimide or copper thickness but vary significantly below this critical value. This shows that silicon is the dominant material in the stack when the chip thickness is above 100 microns but below this thickness, stress is more dependent on copper and polyimide thickness. Thermal performance characterisation showed that for the current module set-up total power to the module rather then power to the individual chip is an important criterion for the selection of thermal management scheme. Changing the thickness of polyimide and copper has little effect on module temperature. Decreasing the chip thickness increases the thermal density and thereby increases the total temperature for the stack for any given power.
UR - https://www.scopus.com/pages/publications/33845593390
U2 - 10.1109/ECTC.2006.1645738
DO - 10.1109/ECTC.2006.1645738
M3 - Conference proceeding
AN - SCOPUS:33845593390
SN - 1424401526
SN - 9781424401529
T3 - Proceedings - Electronic Components and Technology Conference
SP - 728
EP - 733
BT - Proceedings - IEEE 56th Electronic Components and Technology Conference
T2 - IEEE 56th Electronic Components and Technology Conference
Y2 - 30 May 2006 through 2 June 2006
ER -