TY - GEN
T1 - TiAS
T2 - 28th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025
AU - Guha, Krishnendu
N1 - Publisher Copyright:
© 2025 IEEE.
PY - 2025
Y1 - 2025
N2 - Present day real time systems are associated with AI/ML workloads that are essentially executed in edge platforms. To ensure fast execution in such edge platforms, field programmable gate arrays (FPGAs) are deployed by designers that provide hardware acceleration, along with spatio-temporal scheduling. However, vulnerability of hardware like hardware trojans may cause unintentional delays and jeopardize the schedules and ultimately cause malfunction to systems. In the present work, we propose a time aware split computing approach that secures the AI/ML workloads for FPGA based edge platforms against unintentional delays, caused due to the vulnerability of hardware. This is a hybrid offline-online approach. In the offline phase, the split points are determined, along with partitioning the tasks into various splitted subtasks that are scheduled to operate in different FPGA platforms deployed at the edge. For runtime security, we develop low overhead TIme Aware Splitting agents (TiASs) that monitor the behaviour and on detecting erroneous activity, communicate with other agents to outsource the subtasks. In order to do so, it splits the subtasks at potential splitting points. Moreover, to achieve an acceptable quality of service, TiASs perform dynamic clock management to speed up execution of subtasks or preempt low critical optional subtasks. As evident from experimental results, low overhead of proposed security modules and high task success rate depict applicability of proposed mechanism for practical environments.
AB - Present day real time systems are associated with AI/ML workloads that are essentially executed in edge platforms. To ensure fast execution in such edge platforms, field programmable gate arrays (FPGAs) are deployed by designers that provide hardware acceleration, along with spatio-temporal scheduling. However, vulnerability of hardware like hardware trojans may cause unintentional delays and jeopardize the schedules and ultimately cause malfunction to systems. In the present work, we propose a time aware split computing approach that secures the AI/ML workloads for FPGA based edge platforms against unintentional delays, caused due to the vulnerability of hardware. This is a hybrid offline-online approach. In the offline phase, the split points are determined, along with partitioning the tasks into various splitted subtasks that are scheduled to operate in different FPGA platforms deployed at the edge. For runtime security, we develop low overhead TIme Aware Splitting agents (TiASs) that monitor the behaviour and on detecting erroneous activity, communicate with other agents to outsource the subtasks. In order to do so, it splits the subtasks at potential splitting points. Moreover, to achieve an acceptable quality of service, TiASs perform dynamic clock management to speed up execution of subtasks or preempt low critical optional subtasks. As evident from experimental results, low overhead of proposed security modules and high task success rate depict applicability of proposed mechanism for practical environments.
KW - FPGA
KW - Hardware Trojan
KW - Scheduling
KW - Security
KW - Split computing
UR - https://www.scopus.com/pages/publications/105016250498
U2 - 10.1109/ISVLSI65124.2025.11130196
DO - 10.1109/ISVLSI65124.2025.11130196
M3 - Conference proceeding
AN - SCOPUS:105016250498
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
BT - IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025 - Conference Proceedings
PB - IEEE Computer Society
Y2 - 6 July 2025 through 9 July 2025
ER -