Timing-driven power optimisation and power-driven timing optimisation of combinational circuits

Power consumption and timing are two major constraints in digital circuit design. Most optimisation techniques usually focus on only one of these constraints, potentially causing degradation in the other. In this paper we propose timing-driven power or power-driven timing optimisation in order to have balanced timing and power values. The goal is to obtain multi-objective optimisation where the two conflicting objectives are power and timing. In our approach, we have used AND-Inverter graphs (AIGs) for such optimisation. We have annotated the switching activities and arrival times of circuit nodes onto AIGs. Several reordering and restructuring rules are applied on the AIG nodes to minimise switching power or timing. Finally Simulated Annealing and Uniform Cost Search Algorithm are used to reach the minimum switching power (or timing) under given timing (or power) constraints respectively The optimisation tool is implemented in C as a sub-package in ABC. Combinational circuits up to 100,000 gates are used to validate our methodology. On average, we achieved 23.46% power reduction with respect to ABC synthesis scripts, with minimal timing and area overhead. We also achieved an average 15.53% reduction in timing (critical path length) with respect to ABC synthesis scripts, with minimal power and area overhead.