Top-gated MoS2 capacitors and transistors with high-k dielectrics for interface study

  • Peng Zhao
  • , Angelica Azcatl
  • , Pavel Bolshakov-Barrett
  • , Robert M. Wallace
  • , Chadwin D. Young
  • , Paul K. Hurley

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

Top-gated MOS capacitors on bulk MoS2 and transistors of few-layer MoS2 were designed and fabricated. They can be potentially utilized on various TMD and high-k materials for fast and robust electrical characterization. The 3-terminal transistor test structure shows advantages of significant reduction of parasitic effects. C-V and I-V measurements were successfully conducted to characterize few-layer MoS2 transistors with sub-10 nm HfO2 dielectric.

Original languageEnglish
Title of host publication2016 29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages172-175
Number of pages4
ISBN (Electronic)9781467387934
DOIs
Publication statusPublished - 20 May 2016
Event29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016 - Yokohama, Japan
Duration: 28 Mar 201631 Mar 2016

Publication series

NameIEEE International Conference on Microelectronic Test Structures
Volume2016-May

Conference

Conference29th IEEE International Conference on Microelectronic Test Structures, ICMTS 2016
Country/TerritoryJapan
CityYokohama
Period28/03/1631/03/16

Keywords

  • capacitor
  • high-k
  • interface defects
  • Molybdenum disulfide (MoS2)
  • top-gated transistor

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