Towards a compact model for MOSFETs with direct tunneling gate dielectrics

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

A circuit simulation model of a MOSFET with 1.5nm gate oxide is presented. The device characteristics are well described by the model. It also gives useful insight into the flow of current in the device and to the division of current between source and drain. Based on this model a method for the division of gate current between source and drain is proposed for use in the development of a compact MOS model including gate current.

Original languageEnglish
Title of host publicationESSDERC 1999 - Proceeding of the 29th European Solid-State Device Research Conference
EditorsR.P. Mertens, H. Grunbacher, H.E. Maes, G. Declerck
PublisherIEEE Computer Society
Pages488-491
Number of pages4
ISBN (Electronic)2863322451, 9782863322451
Publication statusPublished - 1999
Event29th European Solid-State Device Research Conference, ESSDERC 1999 - Leuven, Belgium
Duration: 13 Sep 199915 Sep 1999

Publication series

NameEuropean Solid-State Device Research Conference
Volume13-15 Sept. 1999
ISSN (Print)1930-8876

Conference

Conference29th European Solid-State Device Research Conference, ESSDERC 1999
Country/TerritoryBelgium
CityLeuven
Period13/09/9915/09/99

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