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Towards energy effective LDPC decoding by exploiting channel noise variability

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

In communication systems, channel quality variation is a well known phenomenon, which fundamentally influences the decoding process. While most of the time, the transmission takes place in good signal to noise conditions, to satisfy QoS requirements in all cases, telecom platforms rely on largely over-designed hardware, which may result in energy waste during most of their operation. In this paper we propose to exploit the channel noise variability and adapt the platform operation conditions such that QoS requirements are satisfied with the minimum energy consumption. In particular, we propose a technique to exploit channel noise variability towards energy effective LDPC decoding amenable to low-energy operation. Endowed with the channel noise variability knowledge, our technique adaptively tunes the operating voltage at runtime, aiming to achieve the optimal tradeoff between decoder performance and power con-sumption, while fulfilling the QoS requirements. To demonstrate the capabilities of our proposal we implemented it and other state of the art energy reduction methods in conjunction with a fully parallel LDPC decoder on a Virtex-6 FPGA. Our experiments indicate that the proposed technique outperforms state of the art counterparts, in terms of energy reduction, with 71% to 76% and 15% to 28%, w.r.t. early termination without and with DVS, respectively, while maintaining the targeted decoding robustness. Moreover, the measurements suggest that in certain conditions Degradation Stochastic Resonance occurs, i.e., the energy consumption is unexpectedly diminished due to the fact that unpredictable underpowered components facilitate rather than impede the decoding process.

Original languageEnglish
Title of host publication2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Conference Proceedings
EditorsLorena Garcia
PublisherIEEE Computer Society
EditionJanuary
ISBN (Electronic)9781479960163
DOIs
Publication statusPublished - 7 Jan 2015
Event2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014 - Playa del Carmen, Mexico
Duration: 6 Oct 20148 Oct 2014

Publication series

NameIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
NumberJanuary
Volume2015-January
ISSN (Print)2324-8432
ISSN (Electronic)2324-8440

Conference

Conference2014 22nd International Conference on Very Large Scale Integration, VLSI-SoC 2014
Country/TerritoryMexico
CityPlaya del Carmen
Period6/10/148/10/14

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