@inbook{97979b0ed90748ccb2494a76a0d4d810,
title = "Tunnel FETs for low power electronics",
abstract = "We report on Tunnel Field-Effect Transistors for low power electronics. Thanks to their potential to reach sub-60mV/dec subthreshold slope, these devices are very attractive for use in circuits with sub-0.5V supply voltage. However, proper device design as well as material choice is not obvious and many implementations have shown larger slope than expected, due to parasitic trap-assisted tunneling conduction. We review work done at imec on tunnelFETs. Initial work was based on vertical nanowire structures using goup-IV semiconductor materials. More recently, implementation of TunnelFETS on III-V materials using a Zn-diffusion approach for source doping was demonstrated with an attractive slope below 60mV/dec. Trap-assisted tunneling is extracted from the devices characteristics based on the activation energy of different conduction mechanisms present in the devices.",
keywords = "steep-slope devices, trap-assisted tunneling, TunnelFET, vertical nanowires, Zn-diffused source",
author = "Anne Vandooren and Alireza Alian and Anne Verhulst and Jacopo Franco and Rita Rooyackers and Quentin Smets and Devin Verreck and Niamh Waldron and Dan Mocuta and Nadine Collaert",
note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016 ; Conference date: 10-10-2016 Through 13-10-2016",
year = "2016",
doi = "10.1109/S3S.2016.7804386",
language = "English",
series = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016",
address = "United States",
}