Abstract
The features of two D flip-flops (DFF) - a constant-load bistable-grated-bipolar (CLBGB) DFF (CMOS latch) and a variable-load bistable-grated-bipolar (VLBGB) DFF were compared. These two DFFs were formed by cascading a pair of master and slave latches. The functions and speed of both types were evaluated by implementing it as a divide-by-two counter. The results showed that BGB DFFs has improved speed over CMOS DFF, which is attributed to the capacitance reduction along the data path by replacing the feedback branches with storage cells.
| Original language | English |
|---|---|
| Pages (from-to) | 305-306 |
| Number of pages | 2 |
| Journal | Electronics Letters |
| Volume | 41 |
| Issue number | 6 |
| DOIs | |
| Publication status | Published - 17 Mar 2005 |