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Ultra Low Latency Hardware Optimised Radix-4 FFT for Optical Wireless FPGA Transceivers Via Hermitian Symmetry Characteristics

  • Michael Codd
  • , Ciara McDonald
  • , Yiyue Jiang
  • , Chunan Chen
  • , Holger Claussen
  • , Miriam Leeser
  • , John Dooley
  • Maynooth University
  • Northeastern University
  • Trinity College Dublin

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

Future telecommunication networks are expected to deliver exponential performance increases across all domains and with the increased prevalence of real-time IoT devices, greater emphasis is placed on reducing the latency of network links. Traditionally, wireless networking requirements have been fulfilled primarily through use of the RF spectrum, which is rapidly approaching saturation and will eventually very likely become insufficient to meet all future network demands. The optical spectrum however offers enormous amounts of unrestricted and unallocated bandwidth. Efficient high-modulation indoor LED lighting fixtures could potentially integrate with and complement the RF spectrum for short to medium distance low latency applications. The Fast Fourier Transform (FFT) is a ubiquitous operation in many communication network topologies. Typically the FFT is computed via serial methods which are optimised for low resource usage, however these architectures fall short of the Ultra Low Latency (ULL) requirements for optical wireless communication. Fully parallel FFT computations can achieve nanosecond latency and tens of gigasamples of throughput, far surpassing serial methods. However, their prohibitively high resource utilisation has limited their practical use. In this work, we introduce a hardware optimised, fully parallel architecture for optical wireless communication which leverages hermitian symmetry characteristics within real-valued optical signals and properties of the discrete DFT to reduce the footprint of a fully parallel FFT on an FPGA. The final architecture is implemented on an AMD RFSoC 2 × 2 and requires only 3 clock cycles to compute a 256 -point real-valued FFT, a 290 fold reduction compared to an equivalent serial model. The design was tested at 122.88 MHz, resulting in a 24 nanosecond latency, demonstrating its potential for use in optical wireless communication and other high-performance 5G+ networks.

Original languageEnglish
Title of host publication2024 IEEE High Performance Extreme Computing Conference, HPEC 2024
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350387131
DOIs
Publication statusPublished - 2024
Event2024 IEEE High Performance Extreme Computing Conference, HPEC 2024 - Virtual, Online
Duration: 23 Sep 202427 Sep 2024

Publication series

Name2024 IEEE High Performance Extreme Computing Conference, HPEC 2024

Conference

Conference2024 IEEE High Performance Extreme Computing Conference, HPEC 2024
CityVirtual, Online
Period23/09/2427/09/24

Keywords

  • Fast Fourier Transform
  • FPGA
  • Hardware Optimisation
  • Low Latency Communication
  • Optical Wireless Communication

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