Ultra low power asynchronous charge sharing logic

Asynchronous logic enables significant power reduction and high robustness in digital design. In this paper, a novel Asynchronous Charge Sharing Logic (ACSL) is proposed to achieve ultra-low dynamic and static power with little trade-off in performance. ACSL combines adiabatic logic with charge sharing technology so that the penalty of power clock generator in adiabatic circuit is eliminated while nearly 50% energy transferring efficiency is obtained. Also, by discharging all internal nodes to ground in idle mode, a saving of 75% of static power of a one-bit full adder is achieved while compared to the popular Domino Differential Cascode Voltage Switch Logic (DDCVSL) adder. Some 8-bit multipliers are built based on ACSL, PFAL (Positive Feedback Adiabatic Logic), DDCVSL and dual-rail Domino logic. All our implementations results are reported for the 45 nm CMOS process. At least 30% dynamic power reduction and more than 24% improvement of the Power-Delay Product are achieved compared to other three types of logic. Significant leakage power reductions of more than 30% can be also achieved.