Ultra low power booth multiplier using asynchronous logic

Jiaoyan Chen; Emanuel Popovici; Dilip Vasudevan; Michel Schellekens

doi:10.1109/ASYNC.2012.15

Ultra low power booth multiplier using asynchronous logic

Jiaoyan Chen
, Emanuel Popovici
, Dilip Vasudevan
, Michel Schellekens

University College Cork

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

Asynchronous logic shows promising applicability in ASIC design due to its potentially low power and high robustness properties. For deep submicron technologies the static power is becoming very significant and many applications require that this power component to be reduced. A new logic called Positive Feedback Charge Sharing Logic (PFCSL) is proposed, which reduces both dynamic and especially static power and also could be implemented with asynchronous logic. This new logic combines adiabatic logic with charge sharing technology avoiding the penalty of power clock generator. A novel 16-by-16-bit Radix-4 Booth Multiplier is built based on PFCSL and implemented in 45nm technology. We achieve around 30% reduction in dynamic power and 60% in static power respectively compared to the same design being implemented using static dual-rail logic. Also, the area of the multiplier is significantly smaller.

Original language	English
Title of host publication	Proceedings - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012
Publisher	IEEE Computer Society
Pages	81-88
Number of pages	8
ISBN (Print)	9780769546889
DOIs	https://doi.org/10.1109/ASYNC.2012.15
Publication status	Published - 2012
Event	2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012 - Copenhagen, Denmark Duration: 7 May 2012 → 9 May 2012

Publication series

Name	Proceedings - International Symposium on Asynchronous Circuits and Systems
ISSN (Print)	2643-1394
ISSN (Electronic)	2643-1483

Conference

Conference	2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012
Country/Territory	Denmark
City	Copenhagen
Period	7/05/12 → 9/05/12

Keywords

Adiabatic logic
Asynchronou logic
Booth multiplier

Access to Document

10.1109/ASYNC.2012.15

Cite this

Chen, J., Popovici, E., Vasudevan, D., & Schellekens, M. (2012). Ultra low power booth multiplier using asynchronous logic. In Proceedings - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012 (pp. 81-88). Article 6243885 (Proceedings - International Symposium on Asynchronous Circuits and Systems). IEEE Computer Society. https://doi.org/10.1109/ASYNC.2012.15

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abstract = "Asynchronous logic shows promising applicability in ASIC design due to its potentially low power and high robustness properties. For deep submicron technologies the static power is becoming very significant and many applications require that this power component to be reduced. A new logic called Positive Feedback Charge Sharing Logic (PFCSL) is proposed, which reduces both dynamic and especially static power and also could be implemented with asynchronous logic. This new logic combines adiabatic logic with charge sharing technology avoiding the penalty of power clock generator. A novel 16-by-16-bit Radix-4 Booth Multiplier is built based on PFCSL and implemented in 45nm technology. We achieve around 30\% reduction in dynamic power and 60\% in static power respectively compared to the same design being implemented using static dual-rail logic. Also, the area of the multiplier is significantly smaller.",

keywords = "Adiabatic logic, Asynchronou logic, Booth multiplier",

author = "Jiaoyan Chen and Emanuel Popovici and Dilip Vasudevan and Michel Schellekens",

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series = "Proceedings - International Symposium on Asynchronous Circuits and Systems",

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Chen, J, Popovici, E, Vasudevan, D & Schellekens, M 2012, Ultra low power booth multiplier using asynchronous logic. in Proceedings - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012., 6243885, Proceedings - International Symposium on Asynchronous Circuits and Systems, IEEE Computer Society, pp. 81-88, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Copenhagen, Denmark, 7/05/12. https://doi.org/10.1109/ASYNC.2012.15

Ultra low power booth multiplier using asynchronous logic. / Chen, Jiaoyan; Popovici, Emanuel; Vasudevan, Dilip et al.
Proceedings - 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012. IEEE Computer Society, 2012. p. 81-88 6243885 (Proceedings - International Symposium on Asynchronous Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

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AB - Asynchronous logic shows promising applicability in ASIC design due to its potentially low power and high robustness properties. For deep submicron technologies the static power is becoming very significant and many applications require that this power component to be reduced. A new logic called Positive Feedback Charge Sharing Logic (PFCSL) is proposed, which reduces both dynamic and especially static power and also could be implemented with asynchronous logic. This new logic combines adiabatic logic with charge sharing technology avoiding the penalty of power clock generator. A novel 16-by-16-bit Radix-4 Booth Multiplier is built based on PFCSL and implemented in 45nm technology. We achieve around 30% reduction in dynamic power and 60% in static power respectively compared to the same design being implemented using static dual-rail logic. Also, the area of the multiplier is significantly smaller.

KW - Adiabatic logic

KW - Asynchronou logic

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ER -

Ultra low power booth multiplier using asynchronous logic

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