Verification of layout efficient shield-based de-embedding techniques for on-wafer HBT characterisation up to 30 GHz

On-wafer measurements play a vital role in device characterization and modelling for advanced high speed devices such as SiGe HBT's and submicron MOSFET's. Unfortunately, due to the lossy nature of Si substrates, extensive, area hungry, de-embedding structures are necessary to separate the intrinsic device characteristics from the extrinsic parasitics. It has been postulated, [1], that the use of shield-based structures may lead to a reduction in the layout-area requirements for de-embedding structures. In this work, we show for the first time that shielding techniques do indeed provide an area saving as high as 40% for the HBT process considered here.