TY - GEN
T1 - Versatile architectures for decoding a class of LDPC codes
AU - Byrne, Andrew
AU - Popovici, Emanuel M.
AU - O'Sullivan, Michael
PY - 2005
Y1 - 2005
N2 - This paper presents a construction for low and high rate Low-Density Parity Check (LDPC) codes, their performance and efficient hard-ware implementation. The problem with decoding for LDPC codes is the linear increase in resource requirements as the size of the parity check matrix increases. This results in a number of issues with regard to practical implementation. These issues include interconnect routing, memory size and parallelism. A construction for low complexity, variable rate LDPC code will be introduced and an architecture that takes advantage of certain properties of this construction is proposed. A versatile LDPC decoding architecture is then evaluated on FPGA.
AB - This paper presents a construction for low and high rate Low-Density Parity Check (LDPC) codes, their performance and efficient hard-ware implementation. The problem with decoding for LDPC codes is the linear increase in resource requirements as the size of the parity check matrix increases. This results in a number of issues with regard to practical implementation. These issues include interconnect routing, memory size and parallelism. A construction for low complexity, variable rate LDPC code will be introduced and an architecture that takes advantage of certain properties of this construction is proposed. A versatile LDPC decoding architecture is then evaluated on FPGA.
UR - https://www.scopus.com/pages/publications/33748988490
U2 - 10.1109/ECCTD.2005.1523112
DO - 10.1109/ECCTD.2005.1523112
M3 - Conference proceeding
AN - SCOPUS:33748988490
SN - 0780390660
SN - 9780780390669
T3 - Proceedings of the 2005 European Conference on Circuit Theory and Design
SP - 269
EP - 272
BT - Proceedings of the 2005 European Conference on Circuit Theory and Design
T2 - 2005 European Conference on Circuit Theory and Design
Y2 - 28 August 2005 through 2 September 2005
ER -