Versatile hardware architectures for GF (pm) arithmetic in public key cryptography

Research output: Contribution to journalArticlepeer-review

Abstract

In this paper new algorithms and versatile hardware architectures for generic computations of the type u = abp / c, u = bp / c and u = ab / c in the Galois field GF (pm) are described. In all cases the hardware operates independently of the defining irreducible polynomial of the field and the same hardware can be used for different field sizes offering full versatility up to a maximum field size. The performance of prototype implementations over Galois fields of characteristic p = 3 are discussed through FPGA implementation.

Original languageEnglish
Pages (from-to)28-35
Number of pages8
JournalIntegration
Volume40
Issue number1
DOIs
Publication statusPublished - Jan 2007

Keywords

  • Flexible GF (p) arithmetic
  • GF (3) cryptographic processor

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