TY - CHAP
T1 - Vertical devices for future nano-electronic applications
AU - Collaert, N.
AU - Veloso, A.
AU - Huynh-Bao, T.
AU - Yakimets, D.
AU - Ivanov, Ts
AU - Ramesh, S.
AU - Matagne, P.
AU - Sibaja-Hernandez, A.
AU - Liu, Z.
AU - Merckling, C.
AU - Waldron, N.
AU - Thean, A.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/12/7
Y1 - 2016/12/7
N2 - In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.
AB - In this work, we will review the advantages and challenges of vertical devices which are seen as possible candidates to continue CMOS scaling. Different integration schemes will be discussed, also addressing the use of novel channel materials like III-V that could benefit from a vertical architecture to relax both gate length and wire diameter. Next to that, layout efficiency and the benefits of vertical MOSFETs for SRAM will be highlighted.
UR - https://www.scopus.com/pages/publications/85010465916
U2 - 10.1109/NMDC.2016.7777076
DO - 10.1109/NMDC.2016.7777076
M3 - Chapter
AN - SCOPUS:85010465916
T3 - Nanotechnology Materials and Devices Conference, NMDC 2016 - Conference Proceedings
BT - Nanotechnology Materials and Devices Conference, NMDC 2016 - Conference Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016
Y2 - 9 October 2016 through 12 October 2016
ER -