Vertical nanowire FET integration and device aspects

A. Veloso; E. Altamirano-Sánchez; S. Brus; B. T. Chan; M. Cupak; M. Dehan; C. Delvaux; K. Devriendt; G. Eneman; M. Ercken; T. Huynh-Bao; Ts Ivanov; P. Matagne; C. Merckling; V. Paraschiv; S. Ramesh; E. Rosseel; L. Rynders; A. Sibaja-Hernandez; S. Suhard; Z. Tao; E. Vecchio; N. Waldron; D. Yakimets; K. De Meyer; D. Mocuta; N. Collaert; A. Thean

doi:10.1149/07204.0031ecst

Vertical nanowire FET integration and device aspects

A. Veloso
, E. Altamirano-Sánchez
, S. Brus
, B. T. Chan
, M. Cupak
, M. Dehan
, C. Delvaux
, K. Devriendt
, G. Eneman
, M. Ercken
, T. Huynh-Bao
, Ts Ivanov
, P. Matagne
, C. Merckling
, V. Paraschiv
, S. Ramesh
, E. Rosseel
, L. Rynders
, A. Sibaja-Hernandez
, S. Suhard

Z. Tao, E. Vecchio, N. Waldron, D. Yakimets, K. De Meyer, D. Mocuta, N. Collaert, A. Thean

Interuniversitair Micro-Elektronica Centrum

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (V_min), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

Original language	English
Title of host publication	Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6
Editors	F. Roozeboom, V. Narayanan, K. Kakushima, P. J. Timans, E. P. Gusev, Z. Karim, S. De Gendt
Publisher	Electrochemical Society Inc.
Pages	31-42
Number of pages	12
Edition	4
ISBN (Electronic)	9781607687146
DOIs	https://doi.org/10.1149/07204.0031ecst
Publication status	Published - 2016
Externally published	Yes
Event	Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 - 229th ECS Meeting - San Diego, United States Duration: 29 May 2016 → 2 Jun 2016

Publication series

Name	ECS Transactions
Number	4
Volume	72
ISSN (Print)	1938-6737
ISSN (Electronic)	1938-5862

Conference

Conference	Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 - 229th ECS Meeting
Country/Territory	United States
City	San Diego
Period	29/05/16 → 2/06/16

Access to Document

10.1149/07204.0031ecst

Cite this

Veloso, A., Altamirano-Sánchez, E., Brus, S., Chan, B. T., Cupak, M., Dehan, M., Delvaux, C., Devriendt, K., Eneman, G., Ercken, M., Huynh-Bao, T., Ivanov, T., Matagne, P., Merckling, C., Paraschiv, V., Ramesh, S., Rosseel, E., Rynders, L., Sibaja-Hernandez, A., ... Thean, A. (2016). Vertical nanowire FET integration and device aspects. In F. Roozeboom, V. Narayanan, K. Kakushima, P. J. Timans, E. P. Gusev, Z. Karim, & S. De Gendt (Eds.), Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 (4 ed., pp. 31-42). (ECS Transactions; Vol. 72, No. 4). Electrochemical Society Inc.. https://doi.org/10.1149/07204.0031ecst

Veloso, A. ; Altamirano-Sánchez, E. ; Brus, S. et al. / Vertical nanowire FET integration and device aspects. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6. editor / F. Roozeboom ; V. Narayanan ; K. Kakushima ; P. J. Timans ; E. P. Gusev ; Z. Karim ; S. De Gendt. 4. ed. Electrochemical Society Inc., 2016. pp. 31-42 (ECS Transactions; 4).

@inproceedings{86cf55f53af24a90b3fcb22beda3168b,

title = "Vertical nanowire FET integration and device aspects",

abstract = "This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30\% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.",

author = "A. Veloso and E. Altamirano-S{\'a}nchez and S. Brus and Chan, \{B. T.\} and M. Cupak and M. Dehan and C. Delvaux and K. Devriendt and G. Eneman and M. Ercken and T. Huynh-Bao and Ts Ivanov and P. Matagne and C. Merckling and V. Paraschiv and S. Ramesh and E. Rosseel and L. Rynders and A. Sibaja-Hernandez and S. Suhard and Z. Tao and E. Vecchio and N. Waldron and D. Yakimets and \{De Meyer\}, K. and D. Mocuta and N. Collaert and A. Thean",

note = "Publisher Copyright: {\textcopyright}The Electrochemical Society.; Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 - 229th ECS Meeting ; Conference date: 29-05-2016 Through 02-06-2016",

year = "2016",

doi = "10.1149/07204.0031ecst",

language = "English",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "4",

pages = "31--42",

editor = "F. Roozeboom and V. Narayanan and K. Kakushima and Timans, \{P. J.\} and Gusev, \{E. P.\} and Z. Karim and \{De Gendt\}, S.",

booktitle = "Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6",

address = "United States",

edition = "4",

}

Veloso, A, Altamirano-Sánchez, E, Brus, S, Chan, BT, Cupak, M, Dehan, M, Delvaux, C, Devriendt, K, Eneman, G, Ercken, M, Huynh-Bao, T, Ivanov, T, Matagne, P, Merckling, C, Paraschiv, V, Ramesh, S, Rosseel, E, Rynders, L, Sibaja-Hernandez, A, Suhard, S, Tao, Z, Vecchio, E, Waldron, N, Yakimets, D, De Meyer, K, Mocuta, D, Collaert, N & Thean, A 2016, Vertical nanowire FET integration and device aspects. in F Roozeboom, V Narayanan, K Kakushima, PJ Timans, EP Gusev, Z Karim & S De Gendt (eds), Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6. 4 edn, ECS Transactions, no. 4, vol. 72, Electrochemical Society Inc., pp. 31-42, Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 - 229th ECS Meeting, San Diego, United States, 29/05/16. https://doi.org/10.1149/07204.0031ecst

Vertical nanowire FET integration and device aspects. / Veloso, A.; Altamirano-Sánchez, E.; Brus, S. et al.
Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6. ed. / F. Roozeboom; V. Narayanan; K. Kakushima; P. J. Timans; E. P. Gusev; Z. Karim; S. De Gendt. 4. ed. Electrochemical Society Inc., 2016. p. 31-42 (ECS Transactions; Vol. 72, No. 4).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - Vertical nanowire FET integration and device aspects

AU - Veloso, A.

AU - Altamirano-Sánchez, E.

AU - Brus, S.

AU - Chan, B. T.

AU - Cupak, M.

AU - Dehan, M.

AU - Delvaux, C.

AU - Devriendt, K.

AU - Eneman, G.

AU - Ercken, M.

AU - Huynh-Bao, T.

AU - Ivanov, Ts

AU - Matagne, P.

AU - Merckling, C.

AU - Paraschiv, V.

AU - Ramesh, S.

AU - Rosseel, E.

AU - Rynders, L.

AU - Sibaja-Hernandez, A.

AU - Suhard, S.

AU - Tao, Z.

AU - Vecchio, E.

AU - Waldron, N.

AU - Yakimets, D.

AU - De Meyer, K.

AU - Mocuta, D.

AU - Collaert, N.

AU - Thean, A.

PY - 2016

Y1 - 2016

N2 - This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

AB - This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

UR - https://www.scopus.com/pages/publications/85010657750

U2 - 10.1149/07204.0031ecst

DO - 10.1149/07204.0031ecst

M3 - Conference proceeding

AN - SCOPUS:85010657750

T3 - ECS Transactions

SP - 31

EP - 42

BT - Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

A2 - Roozeboom, F.

A2 - Narayanan, V.

A2 - Kakushima, K.

A2 - Timans, P. J.

A2 - Gusev, E. P.

A2 - Karim, Z.

A2 - De Gendt, S.

PB - Electrochemical Society Inc.

T2 - Symposium on Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6 - 229th ECS Meeting

Y2 - 29 May 2016 through 2 June 2016

ER -

Veloso A, Altamirano-Sánchez E, Brus S, Chan BT, Cupak M, Dehan M et al. Vertical nanowire FET integration and device aspects. In Roozeboom F, Narayanan V, Kakushima K, Timans PJ, Gusev EP, Karim Z, De Gendt S, editors, Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6. 4 ed. Electrochemical Society Inc. 2016. p. 31-42. (ECS Transactions; 4). doi: 10.1149/07204.0031ecst

Vertical nanowire FET integration and device aspects

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